1. Field of the Invention
The present invention generally relates to a device for controlling a temperature compensated self-refresh period, and more specifically, to a technology which prevents mis-operations of a temperature compensated self-refresh circuit in a low power semiconductor memory device.
2. Description of the Prior Art
Generally, a self-refresh operation refers to an operation performed at every predetermined period (basic period) by a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) in order to maintain data stored in a memory cell at a standby state.
However, unnecessary current is consumed since a refresh period is generated as it is when the self-refresh operation is performed at high temperature.
In order to reduce the unnecessary current, a temperature compensated self-refresh circuit that automatically regulates a self-refresh period depending on temperature change in a chip has been disclosed as shown in FIG. 1.
The conventional temperature compensated self-refresh circuit comprises a comparison unit 1, a reference voltage generating unit 2, a logic unit 3 and a temperature sensing unit 4.
Here, the comparison unit 1 comprises PMOS transistors P1 and P2, NMOS transistors N1˜N3, and capacitors C1 and C2. A common gate of the PMOS transistors P1 and P2 is connected to a drain of the PMOS transistor P2, and a power voltage V is applied to a common source of the PMOS transistors P1 and P2.
The NMOS transistor N1, connected between the PMOS transistor P1 and the NMOS transistor N3, has a gate connected to a node (A). The NMOS transistor N2, connected between the PMOS transistor P2 and the NMOS transistor N3, has a gate connected to a node (B). The NMOS transistor N3, connected between the NMOS transistors N1, N2 and a ground voltage terminal, has a gate to receive a control signal VLR.
The capacitor C1 is connected between the node (A) and the ground voltage terminal, and the capacitor C2 is connected between the node (B) and the ground voltage terminal.
The reference voltage generating unit 2 comprises NMOS transistors N4 and N5 which are connected between a power voltage V terminal and the ground voltage terminal. The NMOS transistor N4, connected between the power voltage V terminal and the node (B), has a gate connected in common to a source. The NMOS transistor N5, connected between the node (B) and the ground voltage terminal, has a gate connected to the node (B).
The logic unit 3 comprises inverters IV1˜IV4, and a NAND gate ND1. The inverters IV1˜IV3 invert and delay an output signal from the comparison unit 1. The NAND gate ND1 performs a NAND operation on a temperature sensing operation signal TEMPON, an oscillating strobe signal TOSCRSTB and an output signal from the inverter IV3. The inverter IV4 inverts an output signal from the NAND gate ND1.
The temperature sensing unit 4 comprises PMOS transistors P3 and P4, NMOS transistors N6˜N8, and an inverter IV5.
Here, the PMOS transistor P3, connected between the power voltage V terminal and a source of the NMOS transistor N6, has a gate to receive an output signal from the inverter IV4. The PMOS transistor P4, connected between the power voltage V terminal and the node (A), has a gate to receive the output signal from the inverter IV4.
The NMOS transistors N6˜N8 are connected serially between the node (A) and the ground voltage terminal. Here, a gate of the NMOS transistor N6 is connected to the node (A), the NMOS transistor N7 has a drain connected in common to a gate, and a gate of the NMOS transistor N8 is connected to the output signal from the inverter IV4. The inverter IV5 inverts the output from the inverter IV4 to output an oscillating signal TEMPOSC.
Hereinafter, the operation of the above-described conventional temperature compensated self-refresh circuit is described.
When the temperature sensing operation signal TEMPON is applied, the node (A) transits from a power voltage level (1.5V) to a floating state. As a result, current applied to the node (A) comes to flow into the ground voltage terminal through the NMOS transistors N6 and N7 that are connected with a diode type.
Thereafter, the node (A) outputs the oscillating signal TEMPOSC at a high pulse when the node (A) is less than a voltage level (0.75V) of the node (B) which is a reference voltage of the comparison unit 1.
Here, when the temperature rises, threshold voltages of the NMOS transistors N6 and N7 which are connected with a two-stages diode structure become lower. As a result, as the current also rises, a voltage level of the node (A) reaches a level of the reference voltage of the comparison unit 1 much faster, so that the oscillating signal TEMPOSC is outputted at the high pulse. Therefore, as the temperature becomes higher, the period of the oscillating signal TEMPOSC becomes faster.
However, in the conventional temperature compensated self-refresh circuit, when the temperature becomes lower, the period of the oscillating signal TEMPOSC which is outputted from the circuit increases with an exponential type. As a result, if the temperature falls below a specific temperature, the oscillating signal TEMPOSC is no longer oscillated. In order to solve the problem, a device for controlling the oscillating strobe signal TOSCRSTB at low temperature to control the oscillating signal TEMPOSC at a predetermined period has been disclosed.
However, the period of the oscillating signal TEMPOSC is dramatically changed at high temperature of more than 100° C., so that a refresh period is not regularly generated. As a result, the self-refresh period varies, and consumption of current (IDD6) becomes larger to cause mis-operations of the self-refresh circuit.